Direct transistor-level layout for digital blocks

Book Cover
Kluwer Academic Publishers,
Pub. Date:
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
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Grouping Information

Grouped Work ID 902b8d55-0439-3b99-96ab-7921628a0abc
Grouping Title direct transistor level layout for digital blocks
Grouping Author gopalakrishnan prakash
Grouping Category book
Last Grouping Update 2018-10-10 01:06:21AM
Last Indexed 2019-03-18 04:32:42AM

Solr Details

accelerated_reader_point_value 0
accelerated_reader_reading_level 0
auth_author2 Rutenbar, Rob A., 1957-
author Gopalakrishnan, Prakash.
author2-role Rutenbar, Rob A.,1957-, SpringerLink (Online service)
author_display Gopalakrishnan, Prakash
available_at_ccu CCU Electronic Resources
detailed_location_ccu CCU Electronic Resources
format_category_ccu eBook
format_ccu eBook
id 902b8d55-0439-3b99-96ab-7921628a0abc
isbn 9781402080630
item_details external_econtent:ils:.b29577354|.i71733954|CCU Electronic Resources||eBook|eBook|1|false|true|SpringerLink||||Available Online||cceb||
itype_ccu E-book
last_indexed 2019-03-18T10:32:42.914Z
lexile_score -1
literary_form Non Fiction
literary_form_full Non Fiction
owning_library_ccu Colorado Christian University Online
owning_location_ccu CCU Electronic Resources
primary_isbn 9781402080630
publishDate 2004
record_details external_econtent:ils:.b29577354|eBook|eBook||English|Kluwer Academic Publishers,|2004.|vii, 125 pages : illustrations ; 25 cm.
recordtype grouped_work
Bib IdItem IdGrouped StatusStatusLocally OwnedAvailableHoldableBookableIn Library Use OnlyLibrary OwnedHoldable PTypesBookable PTypesLocal Url
external_econtent:ils:.b29577354 .i71733954 Available Online Available Online false true false false false true
subject_facet Digital integrated circuits, Electronic books, Integrated circuit layout, Transistor circuits
title_display Direct transistor-level layout for digital blocks
title_full Direct transistor-level layout for digital blocks [electronic resource] / Prakash Gopalakrishnan, Rob A. Rutenbar
title_short Direct transistor-level layout for digital blocks
topic_facet Digital integrated circuits, Integrated circuit layout, Transistor circuits