Direct transistor-level layout for digital blocks

Book Cover
Publisher:
Kluwer Academic Publishers,
Pub. Date:
2004.
Language:
English
Description
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
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Grouping Information

Grouped Work ID902b8d55-0439-3b99-96ab-7921628a0abc
Grouping Titledirect transistor level layout for digital blocks
Grouping Authorgopalakrishnan prakash
Grouping Categorybook
Last Grouping Update2019-12-17 01:50:01AM
Last Indexed2020-01-29 03:10:55AM

Solr Details

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auth_author2Rutenbar, Rob A., 1957-
authorGopalakrishnan, Prakash.
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Bib IdFormatFormat CategoryEditionLanguagePublisherPublication DatePhysical Description
external_econtent:ils:.b29577354eBookeBookEnglishKluwer Academic Publishers, 2004.vii, 125 pages : illustrations ; 25 cm.
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subject_facetDigital integrated circuits
Electronic books
Integrated circuit layout
Transistor circuits
title_displayDirect transistor-level layout for digital blocks
title_fullDirect transistor-level layout for digital blocks [electronic resource] / Prakash Gopalakrishnan, Rob A. Rutenbar
title_shortDirect transistor-level layout for digital blocks
topic_facetDigital integrated circuits
Integrated circuit layout
Transistor circuits